System and method for instruction sets with run-time consistency check

ABSTRACT

A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.

TECHNICAL FIELD

This disclosure relates in general to the field of computer systems and,more particularly, to instruction sets with run-time consistency check.

BACKGROUND

Many electronic devices use processors (e.g., a central processing unit(CPU)) and a memory to perform various functions. For example, embeddedprocessors in certain routers may be responsible for data-planeprocessing tasks and for network traffic flows (propagating through therouters). The processors may facilitate baseline packet routingoperations, including Layer 2 and Layer 3 forwarding, quality-of-service(QoS) classification, policing and shaping, security access controllists (ACLs), and loadbalancing. Due to high consumer demand, there is apush to pack more functionalities into electronic devices, whileconcurrently, device sizes are either remaining constant or becomingsmaller.

As more functionalities are packed into smaller footprints, there is ademand for more efficient and reliable processors that can facilitatethe myriad functionalities of the electronic device. For example,certain processors can consolidate a multitude of customizedpacket-processor cores (e.g., running at 900 MHz to 1.2 GHz) into asingle piece of silicon, and thereby, reducing the use of externalservice blades inside the router. Such high performance processors maybenefit from efficient and robust instruction set architectures forreliable system operations.

BRIEF DESCRIPTION OF THE DRAWINGS

To provide a more complete understanding of the present disclosure andfeatures and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying figures, whereinlike reference numerals represent like parts, in which:

FIG. 1 is a simplified block diagram of one embodiment of a system inaccordance with the present disclosure;

FIG. 2 is a simplified block diagram illustrating example instructionencodings in accordance with the present disclosure;

FIG. 3 is a simplified block diagram of additional details of the systemfor embodiments according to the present disclosure; and

FIG. 4 is a simplified block diagram illustrating example operationalactivities that may be associated with embodiments of the presentdisclosure.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Overview

An example method is provided and includes determining whether aninstruction is a target of a non-sequential fetch operation with anexpected numerical property value. The method can also include avoidingexecution of the instruction if it is the target of the non-sequentialfetch operation (and does not have the expected numerical propertyvalue). Other embodiments may include encoding an instruction having afunctionality that is a target of a non-sequential fetch operation withan expected numerical property value. Instructions with the samefunctionality that are not targets of non-sequential fetch operationsare encoded with a different numerical property value. More specificembodiments may include a numerical property of parity, determiningwhether the instruction is valid, setting status bits, sending aninterrupt to a control processor, and any combination thereof to avoidexecution (and potentially other features).

An example apparatus may include a bitwise exclusive OR (XOR) network(that may include any suitable electronic components and electroniccircuitry), an indicator of a non-sequential fetch operation (where theindicator may include any suitable electronic circuitry and electroniccomponents), and an error detection logic (where logic may include anysuitable code, software, etc.). The apparatus can be configured todetermine whether an instruction is a target of a non-sequential fetchoperation that has an expected numerical property value (and avoidexecution of the instruction if the instruction does not have theexpected numerical property and the instruction is the target of thenon-sequential fetch operation). The apparatus may further include aninstruction memory system configured to store encoded instructions of aninstruction set, a program counter configured to store an address of anext instruction to fetch, an instruction fetch logic configured tofetch an instruction from the instruction memory system corresponding tothe address in the program counter, an instruction decode logicconfigured to decode the instruction, an instruction issue logicconfigured to choose execution of the instruction, a read logicconfigured to read one or more operands based on the instruction, and aninteger instruction logic configured to provide control signals thatdirect the program counter to a non-sequential next address (andpotentially set the indicator when a change in program flow isencountered and other features).

Example Embodiments

Turning to FIG. 1, FIG. 1 is a simplified block diagram of an examplesystem 10 for implementing instruction sets with run time consistencycheck in accordance with one embodiment of the present disclosure. Asused herein, an “instruction set” can be part of computer architecturerelated to programming, including without limitation, native data types,instructions, registers, addressing modes, memory architecture,interrupt and exception handling, and external input/output. Aninstruction set may include specifications for operation codes inmachine language, and native language commands that may be implementedby a particular system, such as a processor. System 10 may encompass anembedded microprocessor in a network processor (e.g., in a router), amicroprocessor in mobile devices, a digital signal processor, a computerprocessor, or other forms of programmable devices such as industrialcontrollers, array processors, and the like, which are capable offetching and executing instructions, as described herein. System 10 mayexecute processes to retrieve an instruction from its memory, determinewhich actions the instruction commands, and execute those actions.

System 10 may include an instruction fetch logic 12, a program counter14, and an instruction memory system 16 coupled to a program counter bus20 and instruction busses 18. An instruction decode logic 22 can includea consistency check module 24 for implementing instruction sets with runtime consistency check. An issue logic 26, a read stage 28, and variousother components may also be included in system 10 to execute encodedinstructions stored in instruction memory system 16.

Consistency check module 24 may detect certain errors corresponding tocertain classes of hardware and software problems that, if leftundetected, could lead to data corruption, router-wide crashes, or othersignificant problems. Without limitation, examples of types of errorsdetected by consistency check module 24 include: software errors incomputed jumps, which result in the execution of unexpectedinstructions; software errors in linking or overlays, which result inthe execution of incorrect instructions; software errors in memorymanagement unit configuration that result in incorrect mappings ofprogram pages to virtual addresses; software errors that cause in-stackcorruption such that an attempt to return to a calling procedure mayresult in the execution of incorrect instructions; software errors injust-in-time (JIT) compiler systems, which cause incorrect instructionsto be generated; hardware errors in instruction cache controls, whichresult in incorrect mapping of program addresses to instruction cachelines; hardware errors that result in multiple bit errors in memorystructures or communication mechanisms, which are undetected by paritychecks, etc. In an example embodiment, consistency check module 24 maydetect unexpected code execution due to hardware, software or linkingproblems within executable code pages. Consistency check module 24 mayperform run-time consistency checking of instructions to determineerrors.

System 10 may be configured with a software development environment thathas software elements to compile a high-level language to assembly code,convert assembly code into binary encoded instructions, determine whichinstructions are likely to be targets of non-sequential fetchoperations, use a particular encoding with a specific numerical propertyfor instructions that are likely to be targets of non-sequential fetchoperations, and use another encoding without the specific numericalproperty for instructions, which are not likely to be a target of anon-sequential fetch operation. The configuration shown in FIG. 1 is forease of description only, and should not be interpreted to limit thebroad scope of the present disclosure. Numerous configurations of thecomponents and communication lines in system 10 are possible, and anysuch permutations are encompassed herein in the present disclosure.

For purposes of illustrating certain example techniques of system 10, itis important to understand the activities associated with a typicalenvironment in which system 10 would operate. The following foundationalinformation may be viewed as a basis from which the present disclosuremay be properly explained. Such information is offered earnestly forpurposes of explanation only and, accordingly, should not be construedin any way to limit the broad scope of the present disclosure and itspotential applications.

Processors, such as microprocessors, may include a variety of logiccircuits fabricated on one or more semiconductor chips. Such logiccircuits typically include a central processing unit (“CPU”) core,memory, and various other components. The logic circuits generallyimplement numerous instruction sets comprising instructions. Aninstruction can encompass an operation of a processor, including datahandling and memory operations (e.g., set a register to a fixed constantvalue, move data from a memory location to a register, read and writedata from hardware devices, etc.), arithmetic and logic operations(e.g., add, subtract, multiply, or divide values of two registers, placethe result in a register, set one or more condition codes in a statusregister, perform bitwise operations, compare two values in registers,etc.), and control flow operations (e.g., branch to another location inthe program and execute instructions there, conditionally branch toanother location if a certain condition holds, etc.). An instruction mayspecify which operations to perform (e.g., add, load, branch, etc.),where to find the operands (e.g., CPU registers, memory cells,input/output locations, etc.), locations to store results (e.g., CPUregister, memory cells, etc.), memory locations or offsets, addressingmodes (e.g., for interpreting operands), and other specifications.

An instruction generally comprises a series of bits of ones and/orzeroes. The size or length of an instruction can vary (e.g., from aslittle as 4 bits in some microcontrollers, to 120 bits in particularsystems). For example, processors used in routers, personal computers,mainframes, and supercomputers may have instruction sizes between 8 and64 bits. Within a given instruction set, different instructions may havedifferent lengths. In some architectures, instructions may be a fixedlength, typically corresponding with that architecture's word size. Inother architectures, instructions may have variable length, typicallyintegral multiples of a byte. An instruction may have various numericalproperties associated with it. For example, parity is a numericalproperty of an instruction that specifies whether the number of ones(1's) in the instruction is an odd or an even number.

Instructions may have different formats or encodings (binaryrepresentation of instructions that a processor executes), for example,I-type instruction (e.g., includes instructions with an immediateoperand, branch instructions, and load and store instructions), R-typeinstruction (e.g., includes arithmetic and logic with operands inregisters, shift instructions, and register direct jump instructions),and J-type instruction (e.g., instructions with far jump instructions).I-type instructions and variations may be used for memory operations,R-type instructions and variations may be used for arithmetic and logicoperations and J-type instructions, and variations may be used for farjump operations.

Instructions may be executed sequentially or non-sequentially. Theprocessor, after executing a sequential instruction, subsequentlyexecutes the following instruction. In contrast, non-sequentialinstruction execution generally causes the processor to execute aninstruction, which is not an immediately following instruction. Examplesof non-sequential instructions include conditional branchinginstructions (e.g., “Jump if Bit Set” instruction), direct branchinginstructions (e.g., “Direct Jump and Call” instruction), returns fromroutines instructions (e.g., returning to the address following theinstruction that called the subroutine), interrupt instructions, etc.

Errors may occur in instruction executions for various reasons. Inparticular, errors may be more likely for non-sequential instructions:causing the microprocessor to incorrectly execute the instructions. Theerror may occur in a branch instruction (e.g., mistaken branch, orbranch to a random address, an error in the branch flag or in a targetaddress, etc.) and by instructions executed earlier than the branchinstruction, such as instructions that generate flags, which affect thebranch instruction.

Conventional control flow checking may be used to detect one or more ofthe branch errors by comparing a runtime signature of a basic block witha pre-computed signature assigned to the basic block. Additionalinstructions may also be used for such methods. Alternatively, errorcorrection codes (ECC) may be used to detect errors, where dedicatederror codes can be added to instructions to detect errors. Memorymanagement units are also used to segregate code to be executed, fromcode that is not to be executed. X-space is an example of how a memorymanagement unit can be used for this purpose. Illegal instructiondetection is another way that unexpectedly executed code can bedetected.

However, such schemes have disadvantages such as using additionalinstructions or dedicated bits (e.g., parity bits) in an instruction.Typically, because the length of an instruction is predetermined and maynot be changed easily for a particular instruction set, the amount ofinformation that may be stored in the instruction may be reduced if oneor more bits are used for dedicated error detection. Therefore, there isa need for error detection methods that do not reduce the amount ofinformation stored in the instruction, while detecting hardware andsoftware errors robustly.

An architecture for instruction sets with run-time consistency check, asoutlined by FIG. 1, can resolve many of these issues (and others).Embodiments according to the present disclosure may provide multipleencodings for each instruction such that more than one parity ispossible for each instruction. Multiple instruction encodings may allowfor arbitrary instructions to be control transfer targets (e.g., targetsof non-sequential fetch operations). According to example embodiments,system 10 may be configured for a specific parity for instructionsexpected to be control transfer targets, and a different parity fornon-control transfer target instructions. In cases where instructionencodings may provide for fields with arbitrary values, it may beconvenient to provide multiple parity versions. In an exampleembodiment, system 10 may provide for valid control transfer targets(e.g., an address of location to jump to) having a specific parity.Assemblers (or other code generators) may use the specific parity fortargets and another parity for the remaining instructions. A controltransfer to an instruction without the proper parity may result in anexception and, further, indicate that an unexpected branch target wasencountered. For example, this could be the result of an incorrectlycoded computed branch, a hardware failure, or a problem during assemblyand linking, etc.

Note that in this Specification, references to various features (e.g.,elements, structures, modules, components, steps, operations,characteristics, etc.) included in “one embodiment”, “exampleembodiment”, “an embodiment”, “another embodiment”, “some embodiments”,“various embodiments”, “other embodiments”, “alternative embodiment”,and the like are intended to mean that any such features are included inone or more embodiments of the present disclosure, but may or may notnecessarily be combined in the same embodiments. Furthermore, the words“optimize,” “optimization,” and related terms are terms of art thatrefer to improvements in speed and/or efficiency of a specified outcomeand do not purport to indicate that a process for achieving thespecified outcome has achieved, or is capable of achieving, an “optimal”or perfectly speedy/perfectly efficient state.

Turning to the infrastructure of FIG. 1, the binary instructionencodings (as defined by the instruction set) are stored in memory, forexample, instruction memory system 16 of FIG. 1. Instruction fetch logic12 can communicate with program counter 14 over program counter bus 20.Program counter 14 stores addresses corresponding to a next instructionto be executed. Program counter bus 20 may convey an instruction addressto instruction fetch logic 12. Program counter bus 20 can also updatefrom instruction fetch logic 12 to program counter 14. For example, forsequential instructions, instruction fetch logic 12 may increment theprogram counter by a constant, and may send the estimated address toprogram counter 14 over program counter bus 20.

Instruction fetch logic 12 can communicate with instruction memorysystem 16 over instruction busses 18. Instruction busses 18 can conveyinstruction addresses from instruction fetch logic 12 to instructionmemory system 16. For example, instruction fetch logic 12 can fetch aninstruction from instruction memory system 16 corresponding to anaddress stored in program counter 14 over instruction busses 18.Instruction busses 18 can convey instructions from instruction memorysystem 16 back to instruction fetch logic 12. Instruction memory system16 may act on addresses from instruction busses 18 to look up data(e.g., using static random access memory (SRAM) or caches) representingthe corresponding instruction. The instruction provided by instructionmemory system 16 may comprise several bytes (e.g., 64 bytes, 128 bytes,etc). Instruction memory system 16 may store encoded instructions of aninstruction set, where the instructions are encoded such that aninstruction having a particular functionality (e.g., arithmetic andlogic operation) that is a target of a non-sequential fetch operation isencoded with an expected numerical property value (e.g., even parity of1), and another instruction having the same functionality that is not atarget of a non-sequential fetch operation is encoded with a differentexpected numerical property value (e.g., even parity of 0).

Instruction fetch logic 12 can extract a particular sequence of bytes(e.g., 4 bytes) that corresponds to one instruction. Instruction fetchlogic 12 may sequence instruction fetches from instruction memory system16, detect exceptions related to instruction fetching, and identifyinstruction boundaries. Instruction fetch logic 12 may send theextracted instruction to instruction decode logic 22 to map the rawinstruction bytes to control signals for the operating system.

Instruction decode logic 22 can interpret the instruction. Instructiondecode logic 22 may comprise consistency check module 24 in certainexample implementations. In operation, consistency check module 24 candetect errors in non-sequential instructions. If an instruction isdetermined to have an error, consistency module 24 may facilitatesuitable alerts or other actions as appropriate and based on particularneeds. Consistency check module 24 may avoid execution of instructionsthat have errors, such as instructions that have an unexpected numericalproperty value.

Instruction decode logic 22 may send the control signals to issue logic26. Issue logic 26 may examine the control signals from instructiondecode logic 22 and look up past history to determine if the instructionrepresented by the control signals should be executed. Issue logic 26may act as a gatekeeper and permit execution of the instruction based ona status of system 10. For example, issue logic 26 may look for pipelinehazards, such as data hazards, structural hazards and control hazards(or branching hazards) that may potentially result in incorrectexecution.

If the instruction may be executed, issue logic 26 is configured totransmit the control signals to read stage 28. Read stage 28 may accessregisters and produce operands 30 for integer instruction logic 32.Integer instruction logic 32 can generate control signals for target bus34 that may direct program counter 14 to a non-sequential next addresswhen a jump, call, return or branch instruction causes a change inprogram flow. As used herein, the term “program flow” refers to theorder in which instructions are executed or evaluated. Typically, aprogram flow is line-by-line (e.g., sequential instructions). Target bus34 may also provide the information to instruction decode logic 22 toenable identifying a first instruction to be decoded from anon-sequential program address.

In example embodiments, each stage of an instruction fetch and execute(e.g., instruction fetch, instruction decode, instruction execute,memory access, etc.) may use one clock cycle as the instruction passesthrough the stages sequentially. In an example architecture withoutpipelining, an instruction fetch-and-execute cycle may take up to fiveclock cycles (e.g., corresponding to instruction fetch, instructiondecode, execution, memory access, and write-back). At the end of thefetch cycle, the address of the next instruction to be executed in thenext fetch cycle may be found in program counter 14.

If needed, operands 30 and/or results may be stored in memory, usingvarious modules and appropriate communication busses, for example,virtual address generation logic 36, micro translation lookaside buffer(TLB) 38, bus VA 40, data memory system 42, bus PA 44, main TLB 46 andmain TLB request and response busses 48. Results may be read back intoread stage 28 from integer instruction logic 32 as appropriate. Resultbusses 50 may also send results back into read stage 28 from the variousmodules appropriately. In an example embodiment, read stage 28 mayaccess registers and produce operands 30 for virtual address generationlogic 36. Results from integer instruction logic 32 and data memorysystem 42 may update read stage 28 via result busses 50. Integerinstruction logic 32 can use operands 30 and signals from instructiondecode logic 22 to evaluate integer operations such as addition,subtraction, shifting and masking. Virtual address generation logic 36may use operands 30 to compute a virtual address, for example usingshifting and addition. The virtual address may be passed to Micro TLB 38over bus VA 40. Micro TLB 38 may read VA 40, convert the virtual addressto a physical address, and place it on PA 44. Data memory system 42 mayact on the physical address from bus PA 44 and operands 30 to performmemory load and store operations. The results from load operations maybe returned to read stage 28 over result busses 50.

Turning to FIG. 2, FIG. 2 illustrates example encodings of instructionsaccording to embodiments of the present disclosure. The exampleencodings illustrate a 32-bit instruction. Other instruction lengths mayalso be used without departing from the scope of the present disclosure.A state-space available for instruction encoding may be a limited andscarce resource in many instruction set architectures. Therefore,according to embodiments of the present disclosure, multiple encodingtechniques may be employed to produce a desired numerical property value(e.g., parity, Hamming distance range, run length maximum of 1 or 0,etc.) depending on the instruction functionality (e.g., memoryoperation, arithmetic operation or far jump operation, etc.) to detectcertain software and hardware errors.

In an example embodiment, an instruction having a particularfunctionality (e.g., addition or memory load operation) that is a targetof a non-sequential fetch operation may be encoded with an expectednumerical property value (e.g., even parity of 1) and anotherinstruction having the same functionality that is not a target of anon-sequential fetch operation may be encoded with a different expectednumerical property value (e.g., even parity of 0). A programmer mayconstruct instructions with an expected numerical property value for theinstruction (e.g., even parity 0), and consistency check module 24 maybe configured to detect a deviation from the expected numerical propertyvalue to indicate an error in the instruction. By using a specificnumerical property value on an instruction (e.g., a first instructionafter a program flow change), numerous software or hardware errors canbe detected at run-time. Detecting these errors can improve reliabilityof the combined hardware and software system because a likelihood ofexecution of unexpected instructions is reduced.

In an example embodiment, where parity is the numerical property ofinterest, an even parity bit generator generates an output of 0 if thenumber of 1's in the input sequence (e.g., instruction) is even and anoutput of 1 if the number of 1's in the input sequence is odd. Theparity value computed over the instruction may be separate (and in someembodiments, additional) from any parity or error checking that may bepresent to detect errors in memory or communication between modulesand/or components in system 10. Further, unlike a parity informationthat may exist in a memory structure or communication path, the computedand expected parity value may not be explicitly represented in thebinary instruction, but may be implicit in how the instruction appearsin a program order of instruction execution. For example, instructionsthat are targets of non-sequential fetch operations may have an expectedparity (e.g., even parity of 1) as opposed to other instructions in theinstruction set.

In an example embodiment, an instruction set may define a subset ofinstructions that can be encoded with an arbitrary parity value. One ormore instructions in the instruction set may change a flow ofinstruction execution from sequential to a non-sequential address.Components of consistency check module 24 may compute parity of aninstruction to be executed, recognize a first instruction to be executedat a non-sequential address, compare the computed parity of theinstruction to an expected value, and determine whether the instructionhas a parity value that matches the expected value.

In the non-limiting implementation of FIG. 2, instruction encodingformat 52 is an example encoding definition for an arithmetic and logicoperation (e.g., integer instruction). Instructions 54 and 56 may beencoded according to instruction format 52. Instruction format 52 mayprovide 5 bits for an instruction type field 60 (e.g. 00000 may indicatean integer instruction logic), 4 bits for opcode field 62 (e.g.,indicating the operation to be performed, such as add, subtract, etc.),7 bits each for destination field (DST) 64, and source operand fields(SRC1 and SRC2) 66 and 68, and 2 bits for spare bits field 70. An evenparity generator may generate a 0 for instruction 54, because the numberof 1's in instruction 54 corresponds to an even number. The even paritygenerator may generate a 1 for instruction 56, because the number of 1'sin instruction 56 corresponds to an odd number.

Instructions 54 and 56 may have identical functionality, but differentparities due to different values in spare bits field 70. If theinstruction comprising the arithmetic and logic operation is a target ofa non-sequential fetch operation, one of the spare bits may be set to 1,resulting in an even parity of 1 (e.g., instruction 56). On the otherhand, if the instruction is not a target of a non-sequential fetchoperation, the one of the spare bits may be set to 0, resulting in aneven parity of 0 (e.g., instruction 54). Thus, in an example embodiment,when coding an arithmetic instruction in a program, a programmer may useinstruction 56 as a target of a non-sequential fetch operation andinstruction 54 otherwise.

Instruction encoding format 72 is an example encoded definition foranother class of instructions (e.g. memory operation type instructions)where multiple values of a field may be defined to modulate the parityof an instruction. Instructions 74 and 76 may be encoded according toinstruction format 72. Instruction encoding format 72 may provide 5 bitsfor an instruction type field 78, 4 bits for opcode field 80 (e.g.,indicating the operation to be performed, such as load, etc.), 7 bitsfor a source or destination operand field (SRC/DST) 81, 14 bits foroffset bits field 82, and 2 bits for size bits field 83. Parity ofinstructions 74 and 76 may be differentiated by instruction type field78. For example, a value of 11110 in instruction type field 78 may causean even parity generator to return 0, whereas a value of 11111 ininstruction type field 78 may cause the even parity generator to return1.

Instructions 74 and 76 may have identical functionality, but differentparities due to different values in instruction type field 78. If theinstruction comprising the memory operation is a target of anon-sequential fetch operation, one of the bits in instruction typefield 78 may be set to 1, resulting in an even parity of 1 (e.g.,instruction 76). On the other hand, if the instruction is not a targetof a non-sequential fetch operation, the one of the bits in instructiontype field 78 may be set to 0, resulting in an even parity of 0 (e.g.,instruction 74). Thus, in an example embodiment, when coding a memoryinstruction in a program, a programmer may use instruction 76 as atarget of a non-sequential fetch operation and instruction 74 otherwise.

Instruction encoding format 84 is an example encoded definition for yetanother class of instructions (e.g., far jump type instructions).Instructions 85 and 86 may be encoded according to instruction format84. Generally, these types of instructions are rarely used. Instructionencoding format 84 may provide for 5 bits for instruction type field 87and 27 bits for signed offset bits field 88. An even parity generatormay return a parity of 0 for instruction 85 and 1 for instruction 86. Ifthe instruction comprising the far jump operation is a target of anon-sequential fetch operation, one of the bits in signed offset bitsfield 88 may be set to 1: resulting in an even parity of 1 (e.g.,instruction 86). On the other hand, if the instruction is not a targetof a non-sequential fetch operation, the one of the bits in signedoffset bits field 88 may be set to 0: resulting in an even parity of 0(e.g., instruction 84). However, these encodings may cause system 10 toperform different actions for the different parities. Thus, thisencoding is not preferentially favored, but may be used depending onparticular needs and considerations. Either these rare instructions canbe avoided as targets of non-sequential fetches or other instructionselsewhere in the code can be adjusted to compensate for the differencein functionality.

The encoding formats, including the instruction length, number offields, and number of bits for each field described herein are forexample purposes only. Numerous other encoding formats with differentinstruction lengths, fields, and/or bits may be possible for aninstruction. All such variations in encoding formats, including numberof fields, length of fields, number of bits, instruction lengths, etc.,are within the scope of this disclosure.

Turning to FIG. 3, FIG. 3 is a simplified block diagram illustrating anexample embodiment of the present disclosure. Consistency check module24 may comprise an input register 90, which holds a new instruction tobe decoded in instruction bits 92, along with a signal in a “valid” 94register indicating that the instruction is valid (e.g., ready to bedecoded). In an example embodiment, valid (register) 94 returns a valueof 1 for a valid instruction, and 0 for an invalid instruction (e.g.,when system 10 is waiting for memory to be restored and instruction maynot be decoded in the meantime). The instruction from instruction bits92 is passed through a bitwise exclusive OR (XOR) network 96 (which caninclude any suitable components). Consistency check module 24 maycompute a numerical property value (e.g., parity) of each instructionusing bitwise XOR network 96. In an example embodiment using parity,bitwise XOR network 96 may return a value of 0 for even parity, and 1for odd parity.

Branch target indication 98 may be a clocked set-reset storage elementthat responds to a program flow change. For example, target indicationfrom target bus 34 may set branch target indication 98 to “set” for afirst non-sequential instruction in a fetch cycle. Thus, the instructionthat is being processed may be a target of a non-sequential flow whenbranch target indication 98 is set. After the instruction is processed(e.g., decoded), branch target indication 98 may be reset to “clear.” Inan example embodiment, when branch target indication 98 is set, anoutput from branch target indication 98 is 1, and when branch targetindication 98 is cleared, the output is 0.

In an example embodiment, the instruction set may be configured suchthat when branch target indication 98 is “set,” a numerical propertyvalue (e.g., even parity) of 1 is expected for the computed numericalproperty value from bitwise XOR network 96. In an example embodiment, avalid signal may cause branch target indication 98 to clear at the endof a clock cycle when any valid instruction is observed, includingsequential instructions or branch targets (e.g., the set and clear aretypically synchronous with the clock).

Error detection logic module 100 may invert the calculated numericalproperty value from bitwise XOR network 96 using inverter 102, thenlogically AND this value with outputs from valid register 94 and branchtarget indication 98 using AND gate 104. According to an exampleembodiment, when a non-sequential valid instruction is encountered, theoutput of branch target indication 98 and valid register 94 may bothbe 1. The output of bitwise XOR network 96 for an error free instructionmay also be 1, which is inverted to 0 by inverter 102. Consequently, ANDgate 104 returns a value of 0 for a valid, error-free non-sequentialinstruction.

On the other hand, if the instruction has an error, the output ofbitwise XOR network 96 may be 0, which may be inverted to 1 by inverter102. Consequently, AND gate 104 returns a value of 1, which may beconfigured to be an error signal that can be used for further actionsthat avoid execution of the instruction, for example, an action to setstatus bits (e.g., status update logic 106), an action to generate anexception (e.g., exception logic 108), action 110 to interrupt a controlprocessor (e.g., interrupt output to a control processor), or acombination thereof. Action 106 may set one or more bits in a statusregister, with or without an exception, to notify software than anunexpected condition was detected.

Action 108 may generate an exception to avoid execution of theinstruction and notify software that an unexpected condition wasdetected. Action 110 may generate a status output signal, with orwithout an exception, to send an interrupt indication to a controlprocessor. The interrupt indication to the control processor may resultin the control processor halting or resetting the programming computingdevice under the direction of supervisor software running on the controlprocessor. Various other actions may also be possible, based onparticular needs and considerations.

In alternate embodiments, an even parity value of 0 may be expected atthe target of a non-sequential address. Instructions that are nottargets of program flow changes may be encoded, wherever possible, witha parity opposed to the expected parity (e.g., even parity of 1). Inother embodiments, some other non-parity numerical property (assumingflexibility for encoding the non-parity numerical property is providedin the instruction set definition) may also be expected (e.g., encodedappropriately) without changing the scope of the present disclosure.Instructions that are not targets of program flow changes may be encodedwithout the numerical property value expected for a non-sequentialaddress target.

Turning to FIG. 4, FIG. 4 is a flowchart illustrating exampleoperational activities that may be associated with embodiments of thepresent disclosure. A method 400 begins at process block 402, when afetch cycle in system 10 is activated. At process block 410, aninstruction to be executed is obtained. In decision block 420, adetermination is made whether the instruction is a target of anon-sequential fetch. If not, (i.e., the instruction is determined to bea target of a sequential fetch), the process reverts to process block410 to obtain the next sequential instruction.

If it is determined that the instruction is a target of a non-sequentialfetch, a numerical property value over the instruction bits iscalculated in process block 430. Next, decision block 440 tests theoutcome of the calculation. If the instruction has the expected property(e.g., numerical property, such as parity, hamming distance, etc.), theprocess reverts to process block 410 to obtain the next instruction. Ifthe instruction does not have the expected property, then a suitableaction that avoids execution of the instruction is generated in processblock 450. The suitable action that is generated may be, for example,throwing an exception, setting status bits, sending an interrupt outputto a control processor, or a combination thereof. A determination ismade in decision block 460 whether the instructions to be decoded areover. If not, the process reverts to process block 410 to obtain thenext instruction. Otherwise, the process ends in termination block 470.

In example implementations, at least some portions of the activitiesrelated to instruction sets with run time consistency check outlinedherein may be implemented using software. In some embodiments, one ormore of these features may be implemented in hardware, provided externalto these elements, or consolidated in any appropriate manner to achievethe intended functionality. System 10 may include software that cancoordinate to achieve the operations as outlined herein. In still otherembodiments, these elements may include any suitable algorithms,hardware, software, components, modules, interfaces, or objects thatfacilitate the operations thereof.

Furthermore, system 10 described and shown herein may also includesuitable interfaces for receiving, transmitting, and/or otherwisecommunicating data or information in a network environment.Additionally, some of the processors and memory elements associated withthe various elements may be removed, or otherwise consolidated such thata single processor and a single memory location are responsible forcertain activities. In a general sense, the arrangements depicted in theFIGURES may be more logical in their representations, whereas a physicalarchitecture may include various permutations, combinations, and/orhybrids of these elements. It is imperative to note that countlesspossible design configurations can be used to achieve the operationalobjectives outlined here. Accordingly, the associated infrastructure hasa myriad of substitute arrangements, design choices, devicepossibilities, hardware configurations, software implementations,equipment options, etc.

In some of example embodiments, one or more memory elements can storedata used for the operations described herein. This includes the memoryelement being able to store encoded instructions, software, logic, orcode to be executed to carry out the activities described in thisSpecification. A processor can execute any type of instructionsassociated with the data to achieve the operations detailed herein inthis Specification. In one example, one or more processors associatedwith system 10 could transform an element or an article (e.g., data)from one state or thing to another state or thing. In another example,the activities outlined herein may be implemented with fixed logic orprogrammable logic (e.g., software/computer instructions executed by aprocessor) and the elements identified herein could include some type ofa programmable processor, programmable digital logic (e.g., a fieldprogrammable gate array (FPGA), an erasable programmable read onlymemory (EPROM), an electrically erasable programmable read only memory(EEPROM)), an ASIC that includes digital logic, software, code,electronic instructions, flash memory, optical disks, CD-ROMs, DVD ROMs,magnetic or optical cards, other types of machine-readable mediumssuitable for storing electronic instructions, or any suitablecombination thereof.

Components in system 10 can include one or more memory elements forstoring information to be used in achieving operations associated withinstruction set run-time consistency check as outlined herein. Thesedevices may further keep information in any suitable type of memoryelement (e.g., random access memory (RAM), read only memory (ROM), fieldprogrammable gate array (FPGA), erasable programmable read only memory(EPROM), electrically erasable programmable ROM (EEPROM), etc.),software, hardware, or in any other suitable component, device, element,or object where appropriate and based on particular needs. Theinformation being tracked, sent, received, or stored in system 10 couldbe provided in any database, register, table, cache, queue, controllist, or storage structure, based on particular needs andimplementations, all of which could be referenced in any suitabletimeframe. Any of the memory items discussed herein should be construedas being encompassed within the broad term ‘memory element.’ Similarly,any of the potential processing elements, modules, and machinesdescribed in this Specification should be construed as being encompassedwithin the broad term ‘processor.’

Note that with the numerous examples provided herein, interaction may bedescribed in terms of two, three, four, or more elements. However, thishas been done for purposes of clarity and example only. It should beappreciated that the system can be consolidated in any suitable manner.In certain cases, it may be easier to describe one or more of thefunctionalities of a given set of flows by only referencing a limitednumber of elements. It should be appreciated that system 10 of theFIGURES and its teachings are readily scalable and can accommodate alarge number of components, as well as more complicated/sophisticatedarrangements and configurations. Accordingly, the examples providedshould not limit the scope or inhibit the broad teachings of system 10as potentially applied to a myriad of other architectures.

It is also important to note that the operations and steps describedwith reference to the preceding FIGURES illustrate only some of thepossible scenarios that may be executed by, or within, the system. Someof these operations may be deleted or removed where appropriate, orthese steps may be modified or changed considerably without departingfrom the scope of the discussed concepts. In addition, the timing ofthese operations may be altered considerably and still achieve theresults taught in this disclosure. The preceding operational flows havebeen offered for purposes of example and discussion. Substantialflexibility is provided by the system in that any suitable arrangements,chronologies, configurations, and timing mechanisms may be providedwithout departing from the teachings of the discussed concepts.

Although the present disclosure has been described in detail withreference to particular arrangements and configurations, these exampleconfigurations and arrangements may be changed significantly withoutdeparting from the scope of the present disclosure. For example,although the present disclosure has been described with reference toinstructions involving certain length (e.g., 32 bits) and instructionformats, system 10 may be applicable to other architectures withdifferent instruction lengths and different formats. Moreover, althoughsystem 10 has been illustrated with reference to particular elements andoperations that facilitate the instruction execution process, theseelements and operations may be replaced by any suitable architecture orprocess that achieves the intended functionality of system 10.

Numerous other changes, substitutions, variations, alterations, andmodifications may be ascertained to one skilled in the art and it isintended that the present disclosure encompass all such changes,substitutions, variations, alterations, and modifications as fallingwithin the scope of the appended claims. In order to assist the UnitedStates Patent and Trademark Office (USPTO) and, additionally, anyreaders of any patent issued on this application in interpreting theclaims appended hereto, Applicant wishes to note that the Applicant: (a)does not intend any of the appended claims to invoke paragraph six (6)of 35 U.S.C. section 112 as it exists on the date of the filing hereofunless the words “means for” or “step for” are specifically used in theparticular claims; and (b) does not intend, by any statement in thespecification, to limit this disclosure in any way that is not otherwisereflected in the appended claims.

1. A method, comprising: determining whether an instruction is a targetof a non-sequential fetch operation; determining whether the instructionhas an expected numerical property value; and avoiding an execution ofthe instruction if the instruction does not have the expected numericalproperty and the instruction is the target of the non-sequential fetchoperation.
 2. The method of claim 1, further comprising: encoding atleast one instruction having a functionality with a first expectednumerical property value, wherein the at least one instruction is atarget of a non-sequential fetch operation; and encoding at leastanother instruction having the functionality with a second expectednumerical property value, wherein the at least another instruction isnot a target of a non-sequential fetch operation.
 3. The method of claim2, wherein the encoding of the at least one instruction comprisessetting a bit in a spare bit field to 1 and the encoding of the at leastanother instruction comprises setting the bit in the spare bit field to0.
 4. The method of claim 2, wherein the encoding of the at least oneinstruction comprises setting a bit in an instruction type field to 1,and the encoding of the at least another instruction comprises settingthe bit in the instruction type field to
 0. 5. The method of claim 1,wherein the numerical property value is parity.
 6. The method of claim5, wherein the expected parity is odd such that an even parity bitgenerator is expected to return an output of 1 for the instruction. 7.The method of claim 1, further comprising: performing an action, whereinthe action is a selected one of a group of actions, the group consistingof: a) throwing an exception; b) setting status bits; and c) sending aninterrupt to a control processor.
 8. The method of claim 1, furthercomprising: determining whether the instruction is valid.
 9. Anapparatus, comprising: a bitwise exclusive OR (XOR) network; anindicator of a non-sequential fetch operation; and an error detectionmodule, wherein the apparatus is configured to perform the operationscomprising: determining whether an instruction is a target of anon-sequential fetch operation; determining whether the instruction hasan expected numerical property value; and avoiding an execution of theinstruction if the instruction does not have the expected numericalproperty and the instruction is the target of the non-sequential fetchoperation.
 10. The apparatus of claim 9, further comprising: aninstruction memory system configured to store encoded instructions of aninstruction set, wherein: at least one instruction having afunctionality is encoded with a first expected numerical property value,and the at least one instruction is a target of a non-sequential fetchoperation; and at least another instruction having the functionality isencoded with a second expected numerical property value, and the atleast another instruction is not a target of a non-sequential fetchoperation.
 11. The apparatus of claim 10, wherein encoding of the atleast one instruction comprises setting a bit in a spare bits field to 1and encoding of the at least another instruction comprises setting thebit in the spare bits field to
 0. 12. The apparatus of claim 10, whereinencoding of the at least one instruction comprises setting a bit in aninstruction type field to 1 and encoding of the at least anotherinstruction comprises setting the bit in the instruction type field to0.
 13. The apparatus of claim 10, further comprising: a program counterconfigured to store an address of a next instruction to fetch; aninstruction fetch logic configured to fetch an instruction from theinstruction memory system corresponding to the address in the programcounter; an instruction decode logic configured to decode theinstruction; an instruction issue logic configured to choose executionof the instruction; a read logic configured to read one or more operandsbased on the instruction; and an integer instruction logic configured toprovide control signals that direct the program counter to anon-sequential next address and set the indicator when a change inprogram flow is encountered.
 14. The apparatus of claim 9, wherein thenumerical property value is parity.
 15. The apparatus of claim 9,wherein the indicator is set if the instruction is a target of anon-sequential operation and the indicator is cleared if the instructionis not a target of a non-sequential operation.
 16. The apparatus ofclaim 9, further comprising: a valid register configured to determine ifthe instruction is valid and clear the indicator at an end of a clockcycle when any valid instruction is observed.
 17. The apparatus of claim9, wherein the error detection module comprises an inverter and an ANDgate, and wherein: an output of the bitwise XOR network comprises aninput to the inverter; and an output of the inverter and an output ofthe indicator comprise inputs to the AND gate.
 18. Logic encoded innon-transitory media that includes code for execution and when executedby a processor is operable to perform operations comprising: determiningwhether an instruction is a target of a non-sequential fetch operation;determining whether the instruction has an expected numerical propertyvalue; and avoiding an execution of the instruction if the instructiondoes not have the expected numerical property and the instruction is thetarget of the non-sequential fetch operation.
 19. The logic of claim 18,wherein the operations further comprise: encoding at least oneinstruction having a functionality with a first expected numericalproperty value, wherein the at least one instruction is a target of anon-sequential fetch operation; and encoding at least anotherinstruction having the functionality with a second expected numericalproperty value, wherein the at least another instruction is not a targetof a non-sequential fetch operation.
 20. The logic of claim 18, whereinthe operations further comprising: determining whether the instructionis valid.